LV5217GP
I 2 C bus transmission method
START condition and STOP condition
When transferring data over an I 2 C bus, SDA must basically be held in certain states while SCL is High, as shown in the
figure below.
SCL
SDA
ts2
th2
Both SCL and SDA are high when not performing data transfer.
When both SCL and SDA are high, changing SDA from high to low generates the START condition and starts access.
Changing SDA from low to high while SCL is high generates the STOP condition and ends access.
SCL
SDA
Start condition
th1
Stop condition
th3
Data transfer and confirmation response
After the START condition is generated, data is transferred one byte (8 bits) at a time. Data can be transferred
continuously for any number of bytes. The ACK signal is sent from the receiving to the transmitting side each time 8 bits
of data are transferred.
The transmitting side releases the SDA line immediately after the SCL clock pulse corresponding to the 8th data transfer
bit as it falls to Low, and the receiving side then sends the ACK signal by setting SDA Low.
After the receiving side sends the ACK signal, if the next byte transfer is still in receive mode, the receiving side releases
the SDA line at the falling edge of the 9th SCL clock.
The I 2 C bus does not have a CE signal, so instead a 7-bit slave address is assigned to each device. The first byte of each
transfer is assigned to this 7-bit slave address and a command (R/W) indicating the transfer direction of the following data.
Note that only Write mode is valid for this IC.
The 7-bit address is transferred in order from the MSB, and the 8th bit is Low to indicate Write mode.
The LV5217GP slave address is prescribed as “1110101.”
Start
M
S
B
Slave address
L
S
B
W
A
C
K
M
S
B
Register address
L
S
B
A
C
K
M
S
B
Data
L
S
B
A
C
K
Stop
SCL
SDA
1 1 1
0 1 0
1
0 0 0
0 0 0
1 0
0 0 0
1 0 0
0 1
No.A0833-11/12
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